Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 25
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
8. Click Next to proceed to the Default Part page (Figure 1-8) where the device that
needs to be targeted can be selected. The Default Part page appears as shown in
Figure 1-8.
X-Ref Target - Figure 1-7
Figure 1-7: Add Constraints (Optional)
X-Ref Target - Figure 1-8
Figure 1-8: Default Part (Default Window)
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