Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 382
UG586 November 30, 2016
www.xilinx.com
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
4. Click Next to proceed to the Project Type page (Figure 3-4). Select the Project Type as
RTL Project because MIG deliverables are RTL files.
5. Click Next to proceed to the Add Sources page (Figure 3-5). RTL files can be added to
the project in this page. If the project was not created earlier, proceed to the next page.
X-Ref Target - Figure 3-4
Figure 3-4: Project Type
X-Ref Target - Figure 3-5
Figure 3-5: Add Sources
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