Xilinx Zynq-7000

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 430
UG586 November 30, 2016
www.xilinx.com
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
X-Ref Target - Figure 3-40
Figure 3-40: RLDRAM II Client Interface Protocol (Four-Word Burst Architecture)
USER?CMD?EN
USER?CMD
USER?ADDR
USER?BA
USER?WR?EN
USER?WR?DATA
USER?WR?DM
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