Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 490
UG586 November 30, 2016
www.xilinx.com
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
3. Apply the settings and select OK.
4. In the Flow Navigator window, select Run Simulation and select Run Behavioral
Simulation as shown in Figure 3-65.
5. Vivado invokes IES and simulations are run in the IES tool. For more information, see the
Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref 8].
For detailed information on setting up Xilinx libraries, see COMPXLIB in the Command Line
Tools User Guide (UG628) [Ref 17] and the Synthesis and Simulation Design Guide (UG626)
[Ref 18]. For simulator tool support, see the Zynq-7000 AP SoC and 7 Series Devices Memory
Interface Solutions Data Sheet (DS176) [Ref 1].
X-Ref Target - Figure 3-68
Figure 3-68: Simulation with IES
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