Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 5
UG586 November 30, 2016
www.xilinx.com
11/19/2014 2.3
Chapter 1
• Updated description in Round-Robin section.
• Updated RTT_WR in Table 1-92: 7 Series FPGA Memory Solution Configuration
Parameters.
• Updated description in Debugging OCLKDELAYED Calibration Failures section.
• Updated Table 1-106: Debug Signals of Interest for OCLKDELAYED Calibration.
•Updated GES time in Calibration Times section.
• Updated bits in left_loss_pb and right_gain_pb in Table 1-109: Debug Signals of
Interest for PRBS Read Leveling Calibration.
10/01/2014 2.2
• Global update to example design link in Files in example_design/sim Directory tables,
updated links in Simulation Flow Using IES and VCS Script Files section, updated
Simulation Flow Using Vivado Simulator section, and updated Simulation Flow Using
QuestaSim section.
Chapter 1
• Updated Reference Clock description in FPGA Option section.
• Updated C_S_AXI_DATA_WIDTH description in Table 1-19: AXI4 Slave Interface
Parameters.
• Updated Fig. 1-50: Clocking Architecture.
• Updated OCLKDELAYED Calibration section.
• Updated Write Path section.
• Added REF_CLK_MMCM_IODELAY_CTRL in Table 1-92: 7 Series FPGA Memory
Solution Configuration Parameters.
• Added note for nBANK_MACHS in Table 1-93: Embedded 7 Series FPGAs Memory
Solution Configuration Parameters.
• Added row and updated Table 1-94: DDR2/DDR3 SDRAM Memory Interface Solution
Pinout Parameters
• Updated CK/CK# bullet in Trace Length section.
• Updated Table 1-102: DDR2/DDR3 Debug Signals.
• Updated debug signals in Table 1-112: Debug Signals Used for Checking and Varying
Read/Write Timing.
Continued
Chapter 2
• Added Bank Sharing Among Controllers section in Design Guideline section.
Chapter 3
• Added Bank Sharing Among Controllers section in Design Guideline section.
Chapter 4
• Updated Figs. 4-57 to 4-59 and Figs. 4-62 to 4-63.
• Updated 2:1 description in Write Path section.
• Updated rules in Termination section.
Date Version Revision