Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 6
UG586 November 30, 2016
www.xilinx.com
06/04/2014 2.1
Chapter 1
• Added reference to data sheet in Features section.
• Added Important note about Data Mask in Controller Options section.
• Added note in Precharge Policy section.
• Added PRBS_SADDR_ MASK)POS to Table 1-11: Traffic Generator Parameters Set in
the example_top Module.
• Updated IDELAYCTRL frequency in IDELAYCTRL section.
• Updated IDELAY Reference Clock section.
• Updated PRBS Read Leveling section.
• Updated CL description for DDR3 in Table 1-93: Embedded 7 Series FPGAs Memory
Solution Configuration Parameters.
• Updated package length descriptions in Trace Length section.
• Added simulation description in Note in Debugging DDR3/DDR2 Designs.
• Updated description in Debugging PRBS Read Leveling Failures section.
• Updated Table 109: Debug Signals of Interest for PRBS Read Leveling Calibration.
Chapter 2
• Added reference to data sheet in Introduction section.
• Updated package length descriptions in Trace Length Requirements section.
• Added CPT_CLK_SEL_* row in Table 2-11: QDR II+ SRAM Memory Interface Solution
Pinout Parameters.
• Added simulation description in Note in Debugging QDR II+ Designs.
Chapter 3
• Added reference to data sheet in Features section.
• Added note in Memory Controller section.
• Added PRBS_SADDR_ MASK)POS to Table 3-8: Traffic Generator Parameters Set in the
example_top Module.
• Updated rules and package length descriptions in Trace Length Requirements
section.
• Added simulation description in Note in Debugging RLDRAM II and 3 Designs.
Continued
Chapter 4
• Added note in Precharge Policy section.
• Added PRBS_SADDR_ MASK)POS to Table 4-11: Traffic Generator Parameters Set in
the example_top Module.
• Updated package length descriptions in Trace Length Requirements section.
• Added simulation description in Note in Read Path section.
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