Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 7
UG586 November 30, 2016
www.xilinx.com
04/02/2014 2.0
Chapter 1
• Updated book to DQS.
• Updated Table 1-4: Files in example_design/sim Directory.
• Updated file description in Simulation Flow Using IES and VCS Script Files section.
• Added No Buffer description in the System Clock bullet in FPGA Options section.
• Updated mc_data_offset description in Memory Controller to Calibration Logic
Interface Signals table.
• Added MPR read leveling process in Multi-Purpose Register Read Leveling section.
• Updated Temperature Monitor section.
• Added tempmon information in Physical Layer Interface (Non-Memory Controller
Design) section.
• Added description in address and control signals in Termination section for DDR3.
• Added description in address and control signals and updated CKE signal bullet in
Termination section for DDR2.
• Added CK description in Trace Lengths section.
• Added new code constraints for DDR3/DDR2 Configuration sections.
• Added Clocking section.
• Updated ocal signals in Table 1-102: DDR2/DDR3 Debug Signals.
Chapter 2
• Added new code constraints in Configuration section.
• Updated Table 2-3: Files in example_design/sim Directory.
• Updated file description in Simulation Flow Using IES and VCS Script Files section.
Chapter 3
• Added new code constraints in Configuration section.
• Updated Table 3-3: Files in example_design/sim Directory.
• Added important note on write and read commands in Interfacing with the Core
through the Client Interface section.
• Updated option for MRS_RD_LATENCY in RLDRAM II Memory Interface Solution
Configurable Parameters table.
• Updated file description in Simulation Flow Using IES and VCS Script Files section.
Chapter 4
• Added new code constraints in Configuration section.
• Updated Table 4-4: Files in example_design/sim Directory.
• Updated file description in Simulation Flow Using IES and VCS Script Files section.
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