Xilinx Zynq-7000

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 50
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
2. Click Out-of-Context Settings to configure generation of synthesized checkpoints. To
enable the Out-of-Context flow, enable the check box. To disable the Out-of-Context
flow, disable the check box. The default option is “enable” as shown in Figure 1-30.
3. MIG core designs comply with “Hierarchical Design" flow in Vivado. For more
information, see the Vivado
Design Suite User Guide: Hierarchical Design (UG905) [Ref 5]
and the Vivado Design Suite Tutorial: Hierarchical Design (UG946) [Ref 6].
X-Ref Target - Figure 1-30
Figure 1-30: Out-of-Context Settings Window
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