Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 52
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Design generation from the MIG tool can be generated using the Create Design flow or
the Verify Pin Changes and Update Design flows. There is no difference between the
flow when generating the design from the MIG tool. Irrespective of the flow by which
designs are generated from the MIG tool, the XCI file is added to the Vivado tool
project. The implementation flow is the same for all scenarios because the flow depends
on the XCI file added to the project.
6. All MIG generated user design RTL and XDC files are automatically added to the project.
If files are modified and you wish to regenerate them, right-click the XCI file and select
Generate Output Products (Figure 1-33).
X-Ref Target - Figure 1-32
Figure 1-32: Vivado Tool Project Sources Window
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