Xilinx Zynq-7000 - Page 53

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 53
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
7. Clicking the Generate Output Products option brings up the Manage Outputs window
(Figure 1-34).
X-Ref Target - Figure 1-33
Figure 1-33: Generate RTL and Constraints
X-Ref Target - Figure 1-34
Figure 1-34: Generate Window
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