Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 674
UG586 November 30, 2016
www.xilinx.com
Appendix A: General Memory Routing Guidelines
12. For ADDR/CMD/CTRL V
TT
termination, every four termination resistors should be
accompanied by one 1.0 µF capacitor, physically interleaving among resistors, as shown
in Figure A-6.
X-Ref Target - Figure A-6
Figure A-6: Example of V
TT
Termination Placement
UG583_c2_17_050614
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Xilinx Zynq-7000 Specifications

General

Series	Zynq-7000
Number of Cores	Dual-core
Processor Speed	Up to 1 GHz
Device Type	SoC
Logic Cells	Up to 350K
DSP Slices	Up to 900
External Memory Interfaces	DDR3, DDR2, LPDDR2
I/O Standards	LVCMOS, HSTL, SSTL
Operating Temperature	-40°C to +100°C (Industrial), 0°C to +85°C (Commercial)
Package Options	Various BGA packages
I/O Voltage	3.3V