Analog Devices ADuCM356 User Manual

Reference Manual ADuCM356
USE CASE CONFIGURATIONS
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ment technique is a ratiometric measurement where an impedance
measurement is completed on a known, fixed external R
CAL
sepa-
rately to the measurement of the impedance of the sensor.
In this example configuration, the impedance measurement is taken
via the SE0 electrode using Electrochemical Sensor Channel 0. In
Figure 41, Figure 42, and Figure 43, an AC signal of amplitude ±10
mV p-p is coupled onto a DC sensor biased to 0 V (V
BIAS
− V
ZERO
= 0). However, the DC sensor common-mode voltage is 1.1 V. The
AC signal amplitude can be increased to 15 mV.
The high-speed DAC full-scale output with the attenuator on is
approximately ±607 mV/40 = ±15.1 mV p-p. The voltage to the ADC
is calculated as ±15.1 mV/R
LOAD
× R
TIA
. R
LOAD02
is fixed at 100
Ω, which gives a current of approximately 150 μA across R
TIA
. The
testing featured in this reference manual is designed for an ADC
voltage of ±750 mV. As such, set R
TIA
= 5 kΩ.
The impedance measurement is performed in five steps, detailed in
the following sections. The following steps assume a sensor with a
0 V bias requirement between the reference electrode and working
electrode of a 3-electrode electrochemical sensor.
Step 1: Initialize ADuCM356 for Impedance
Measurement
The electrochemical sensor remains biased via the low-power po-
tentiostat loop. To configure the ADC and high-speed DAC operat-
ing mode, perform the following steps:
1. Configure the ADC and DAC circuits for low-power mode to
minimize current consumption by clearing PMBW, Bit 0 = 0.
2. Set Bit 20, Bit 15, Bit 14, and Bits[11:5] of the AFECON register
to 1 to enable high-speed DAC and ADC references, the high-
speed DAC excitation amplifier and buffer, and DFT hardware
accelerator. The waveform generator also must be enabled. Bit
21 is set when using a sensor with a DC bias voltage >0 V.
3. Enable chop mode on the ADC input buffer when measuring
signals <80 kHz. ADCBUFCON, Bits[3:0] = 0x4 enable the ADC
front-end buffer and PGA chop. When measuring signals >80
kHz (as in high-power mode), disable chopping on the ADC
input buffer. ADCBUFCON, Bits[3:0] = 0xF disable ADC input
chopping.
To set up the ADC, configure and calibrate the ADC. Ideally,
calibrate the ADC as a current input (high-speed TIA) with the
desired R
TIA
and ADC PGA gain settings. See the ADC Calibration
section for further details. Configure the ADC output data to go to
the DFT block and configure the number of samples used by the
DFT block in the DFTCON register.
To set up the high-speed DAC, first turn on the high-speed DAC.
Use the waveform generator to generate a sine wave of the desired
frequency and amplitude by appropriately configuring the following
registers:
► HSDACCON. Configure the gain settings.
► PMBW, Bits[3:2]. Use this register to configure the reconstruction
filter settings.
► WGCON. Main waveform control register.
► WGFCW. Configures the frequency of the AC sine wave. If
necessary, adjust the WGPHASE, WGOFFSET, and WGAMPLI-
TUDE registers.
► DACDCBUFCON. Select low-power DAC0 or low-power DAC1
as the DC level of the common-mode voltage excitation amplifi-
ers.
After turning on the high-speed DAC, calibrate the high-speed
DAC output if necessary (optional). The high-speed DAC can be
calibrated to remove the offset error by setting the output code to
0x800, as follows:
► Connect the excitation amplifier to R
CAL
.
► Measure the differential voltage across R
CAL
by selecting the
ADC inputs as the N node and P node of the excitation amplifier:
ADCCON, Bits[12:0] = 0x1424. There are four offset calibration
registers, DACOFFSET, DACOFFSETATTEN, DACOFFSETHP,
and DACOFFSETATTENHP. The relevant register depends on
the excitation amplifier gain setting and whether the device is in
low or high-power mode. See Table 127.
To set up the potentiostat circuit for impedance measurement,
ensure that the low-power DACs are on, with the VBIAS0 and
VZERO0 outputs set to give the same voltage on the RE0 and SE0
pins. By default, leave the electrochemical sensor fully biased by
the low-power potentiostat loop. Using a potentiostat circuit for im-
pedance measurement uses the same settings as hibernate mode
and for measuring a DC current output (LPTIASW0 = 0x302C).
The following code is an example of how to configure the switches
in the low-power loop:
AfeLpTiaSwitchCfg (channel,
SWMODE_NORM); // Low Power
Loop Normal switch settings (0x302C)
To set up the high-speed TIA for impedance measurement, perform
the following steps:
1. Select the R
TIA
values, power setting, and bias voltage source
for the high-speed TIA. The HSRTIACON register configures
the high-speed TIA parallel capacitor and the main R
TIA
resistor.
The HSTIACON register configures the power mode for the
high-speed TIA. Clear HSTIACON, Bits[6:2] = 00000 for impe-
dance measurements ≤80 kHz. Bits[1:0] are 00.
2. Select the high-speed TIA as the ADC input, as modeled in the
following code.
AfeAdcChan(MUXSELP_HSTIA_P,
MUXSELN_HSTIA_N); //Select
HSTIA output as ADC input versus HSTIA_N to
the ADC

Analog Devices ADuCM356 Specifications

General

Brand	Analog Devices
Model	ADuCM356
Category	Microcontrollers
Language	English

Summary

PREFACE

SCOPE

Provides a detailed description of the functionality and features of the ADuCM356.

CLOCKING ARCHITECTURE

DIGITAL DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the digital die system clock.

ANALOG DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the analog die system clock.

POWER MANAGEMENT UNIT

Active Mode

Describes the fully active operating mode where the Arm Cortex-M3 executes from flash and SRAM.

Flexi Mode

Describes the mode where the Arm Cortex-M3 is disabled, allowing peripherals to operate.

Hibernate Mode

Describes the low-power mode where the digital core and most analog blocks are powered down.

SYSTEM RESETS

DIGITAL DIE RESET OPERATION

Explains the reset sources and operation for the digital die, including software resets.

PROGRAMMING, PROTECTION, AND DEBUG

Debug Features

Details the SWD port, flash patch breakpoints, and data watchpoint/trigger units for debugging.

SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS

CORTEX-M3 AND FAULT MANAGEMENT

Describes the system exceptions and fault handling features integrated with the Cortex-M3 processor.

ANALOG DIE CIRCUITRY SUMMARY

ADC, HIGH-SPEED DAC, AND ASSOCIATED AMPLIFIERS OPERATING MODE CONFIGURATION

Configures the operating modes for ADC, High-Speed DAC, and associated amplifiers.

ADC CIRCUIT

ADC CIRCUIT FEATURES

Lists the key features of the ADuCM356's fast multichannel, 16-bit ADC.

LOW-POWER POTENTIOSTAT AMPLIFIERS AND LOW-POWER TIAS

LOW-POWER POTENTIOSTAT AMPLIFIERS

Details the two low-power potentiostat amplifiers for setting external sensor bias voltage.

HIGH-SPEED DAC CIRCUITS

HIGH-SPEED DAC OUTPUT SIGNAL GENERATION

Explains how to generate high-speed DAC output voltage via direct write or waveform generator.

PROGRAMMABLE SWITCHES CONNECTING THE EXTERNAL SENSOR TO THE HIGH-SPEED DAC AND HIGH-SPEED TIA

DX SWITCHES

Selects pins for the high-speed DAC excitation amplifier output, used for impedance measurements.

SEQUENCER

SEQUENCER COMMANDS

Describes the two types of commands: write commands and timer commands (wait, timeout).

SLEEP AND WAKE-UP TIMER

CONFIGURING A DEFINED SEQUENCE ORDER

Defines the order of sequence execution periodically using the SEQORDER register.

USE CASE CONFIGURATIONS

HIBERNATE MODE WHILE MAINTAINING A DC BIAS TO THE SENSOR

Details setup for hibernate mode while maintaining sensor bias voltage.

DMA CONTROLLER

DMA FEATURES

Lists the features of the ADuCM356's dedicated and independent DMA channels.

FLASH CONTROLLER

SUPPORTED COMMANDS

Summarizes the commands supported by the flash controller for read, write, erase, and signature operations.

REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC)

COMMAND REGISTER

Allows execution of specified flash commands like write, erase, abort, and signature generation.

DIGITAL INPUTS AND OUTPUTS

DIGITAL INPUTS AND OUTPUTS OPERATION

Explains how to configure, read, and write digital input and output pins.

I2C SERIAL INTERFACE

I2C OPERATION

Details the steps required to run the I2C peripheral, including startup and modes.

SERIAL PERIPHERAL INTERFACES

SPI OPERATION

Describes the operation of the SPI interface, including initiator and target modes.

REGISTER SUMMARY: SPI0/SPI1

STATUS REGISTERS

Provides status information for SPI0 and SPI1, including ready, overflow, and error conditions.

REGISTER DETAILS: UART

INTERRUPT ENABLE REGISTER

Configures which interrupt sources generate an interrupt for the UART.

DIGITAL DIE GENERAL-PURPOSE TIMERS

GENERAL-PURPOSE TIMER OPERATIONS

Explains the operation of timers in free running mode and periodic mode.

REGISTER SUMMARY: ANALOG DIE GENERAL-PURPOSE TIMERS

CONTROL REGISTER

Controls timer operation, including clock source, mode, and event selection.

REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER

STATUS 0 REGISTER

Provides status information for WUT operation, including synchronization and pending writes.

CYCLIC REDUNDANCY CHECK

CRC OPERATING MODES

Details the core access and DMA access modes for CRC calculation.

REGISTER SUMMARY: CRC

CRC CONTROL REGISTER

Controls the CRC peripheral, including enabling, mirroring, and calculation order.

HARDWARE DESIGN CONSIDERATIONS

SERIAL WIRE DEBUG INTERFACE

Describes the SWD interface for debugging and programming, replacing JTAG.