Safran CORTEX Series - Page 263

HIGH DATA RATE RECEIVER
HDR-4G+ USER’S MANUAL
Ref. DTU 100782
Is.Rev 3.5
Date: June 1, 2021
© Safran Data Systems – IMP000074 e14r1
This document is the property of Safran Data Systems.
It cannot be duplicated or distributed without expressed written consent.
Page 263
 Playback Split2 To be used jointly with the Playback function
Note: DPU A and DPU C are connected to DMU 1. DPU B and DPU D are connected
to DMU 2
PLL BW AUTO
Selection of the PLL BW automatic adjustment.
If not selected , a value must be set from 1 to 255, with unit: 0.01 % of the bit rate
EBN0 MIN AUTO
Selection of the automatic adjustment of the acquisition threshold.
If not selected , a value must be set from –3 to 10 dB, with unit: 1 dB
In OQPSK mode, the following additional parameters appear at the GUI for controlling the I/Q delay
compensation:
OQPSK I/Q DELAY
OQPSK I/Q delay compensation:
 OFF No compensation
 ON (Auto) Automatic compensation
 ON (Fixed) Fixed compensation (see I / Q shift parameter)
I/Q SHIFT
When OQPSK I/Q DELAY is set to ON (Fixed):
I/Q delay compensation: enter any value from -0.25 to +0.25 (symbol)
Enter 0 for no compensation (optimal OQPSK)
Important: in UQPSK (AQPSK, AUQPSK, AUSQPSK) mode, parameters BIT RATE, PCM CODE
and OUTPUT CLOCK described here above are for the I Channel. The following additional parameters
appear at the GUI for controlling the Q Channel:
BIT RATE Q
Telemetry bit rate for the Q Channel. Expressed in bps. Enter any value from
1e6 to 480.e6 (model dependent)
In AQPSK mode, the I Channel bit rate is supposed to be higher or equal to the
Q Channel bit rate.
PCM CODE Q
PCM code on the Q Channel: NRZ-L/M/S, DNRZ, Bi-P-L/M/S
OUTPUT CLOCK Q
Clock polarity for the Q Channel: Normal or Inverted
I/Q RATIO
Power ratio between I Channel & Q Channel in dB: from 0 to 100