Xilinx Zynq-7000 - Page 22

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 22
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
3. Click Next to proceed to the Project Name page (Figure 1-3). Enter the Project Name
and Project Location. Based on the details provided, the project is saved in the
directory.
X-Ref Target - Figure 1-2
Figure 1-2: Create a New Vivado Tool Project
X-Ref Target - Figure 1-3
Figure 1-3: Project Name
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