Xilinx Zynq-7000 - Page 27

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 27
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
9. Click Next to open the New Project Summary page (Figure 1-11). This includes the
summary of selected project details.
10. Click Finish to complete the project creation.
X-Ref Target - Figure 1-10
Figure 1-10: Default Part Boards Option
X-Ref Target - Figure 1-11
Figure 1-11: New Project Summary
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