Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 278
UG586 November 30, 2016
www.xilinx.com
Chapter 2: QDR II+ Memory Interface Solution
5. Click Next to proceed to the Add Sources page (Figure 2-5). RTL files can be added to
the project in this page. If the project was not created earlier, proceed to the next page.
X-Ref Target - Figure 2-5
Figure 2-5: Add Sources
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