Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 386
UG586 November 30, 2016
www.xilinx.com
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
9. Click Next to open the New Project Summary page (Figure 3-11). This includes the
summary of selected project details.
10. Click Finish to complete the project creation.
X-Ref Target - Figure 3-10
Figure 3-10: Default Part Boards Option
X-Ref Target - Figure 3-11
Figure 3-11: New Project Summary
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