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Xilinx Zynq-7000 User Manual

Xilinx Zynq-7000
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Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 520
UG586 November 30, 2016
www.xilinx.com
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
6. Click Next to open the Add Existing IP (Optional) page (Figure 4-6). If the IP is already
created, the XCI file generated by the IP can be added to the project and the previous
created IP files are automatically added to the project. If the IP was not created earlier,
proceed to the next page.
7. Click Next to open the Add Constraints (Optional) page (Figure 4-7). If the constraints
file exists in the repository, it can be added to the project. Proceed to the next page if
the constraints file does not exist.
X-Ref Target - Figure 4-6
Figure 4-6: Add Existing IP (Optional)
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Xilinx Zynq-7000 Specifications

General IconGeneral
SeriesZynq-7000
Number of CoresDual-core
Processor SpeedUp to 1 GHz
Device TypeSoC
Logic CellsUp to 350K
DSP SlicesUp to 900
External Memory InterfacesDDR3, DDR2, LPDDR2
I/O StandardsLVCMOS, HSTL, SSTL
Operating Temperature-40°C to +100°C (Industrial), 0°C to +85°C (Commercial)
Package OptionsVarious BGA packages
I/O Voltage3.3V

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