Xilinx Zynq-7000

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 544
UG586 November 30, 2016
www.xilinx.com
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
8. All user-design RTL files and constraints files (XDC files) can be viewed in the Sources >
Libraries tab (Figure 4-33).
X-Ref Target - Figure 4-32
Figure 4-32: Generate Window
X-Ref Target - Figure 4-33
Figure 4-33: Vivado Project – RTL and Constraints Files
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