Protocol analysis
R&S
®
RTE
523User Manual 1326.1032.02 ─ 20
●
ACKnowledge bits: is issued by the receiver of the previous byte if the transfer was
successful
Exception: At read access, the master terminates the data transmission with a
NACK bit after the last byte.
●
Data: several data bytes with an ACK bit after every byte
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Stop condition: a rising slope on SDA while SCL is high
Figure 13-1: I2C writes access with 7-bit address
Address types: 7-bit and 10-bit
Slave addresses can be 7 bits or 10 bits long. A 7-bit address requires 1 byte, 7 bits for
the address followed by the R/W bit.
A 10-bit address for write access requires 2 bytes: the first byte starts with the reserved
sequence 11110, followed by the two MSB of the address and the write bit. The second
byte contains the remaining 8 LSB of the address. The slave acknowledges each
address byte.
Figure 13-2: 10-bit address, write access
A 10-bit address for read access requires 3 bytes. The first 2 bytes are identical to the
write access address. The third byte repeats the address bits of the first byte and sets
the read bit.
Figure 13-3: 10-bit address, read access
Trigger
The R&S RTE can trigger on various parts of I²C messages. The data and clock lines
must be connected to the input channels, triggering on math and reference waveforms
is not possible.
You can trigger on:
●
Start or stop condition
I²C (option R&S
RTE-K1)
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