Rohde & Schwarz SMU200A - Page 352

Instrument Function
R&S
®
SMU200A
332Operating Manual 1007.9845.32 ─ 15
In the following example, the diagram shows the output signals of an 8-PSK modulation
(3 bits per symbol) on the serial DATA interface. The positive edge of the clock is always
used when outputting data. The data source is a data list with 15 bits = 001 010 100 101
110 (5 symbols).
Fig. 5-27: Output signal on the serial data interface and clock output signals on the AUX I/O interface
There is a maximum data rate above which serial data processing becomes impossible.
This data rate can be found in the data sheet. If the rate is exceeded the DATA connector
becomes high-impedance, and the output on the CLOCK connector is the symbol clock
instead of the bit clock.
In the following example, the diagram shows the output signals of an 8-PSK modulation
(3 bits per symbol) on the parallel interface. The data source is a data list with 15 bits =
001 010 100 101 110 (5 symbols).
Fig. 5-28: Data and clock output signals on the parallel AUX I/O interface
In order for parallel external data to be retrieved correctly the rising edge of the symbol
clock must be used, since the timing between the falling edge of the symbol clock and
the data switch on the parallel interface is undefined.
Internal Clock and External Synchronous Data
External serial data
When serial data for "Custom Digital Modulation" is being fed in via the DATA connector
on the front panel, the symbol clock acts as a scanning pulse (strobe) so as to mark the
least significant bit in a symbol.
The clock signals are output on the CLOCK and CLOCK OUT connectors (front panel
and rear panel respectively, choice of bit clock or symbol clock on the latter) and on the
BITCLK or SYMBCLK pins on the AUX I/O interface. Optimum timing is achieved from
using the output signal on the CLOCK connector on the front panel. The setup and hold
times (see following diagram, tsetup and thold) that must be maintained in the R&S Signal
Generator to ensure that the serial data is accepted correctly can be found in the data
sheet.
The following diagram illustrates the timing ratios between data and clock when serial
data is being supplied from an external source and the internal clock source is being used.
Baseband Signal - Baseband Block