Instrument Function
R&S
®
SMU200A
333Operating Manual 1007.9845.32 ─ 15
Fig. 5-29: External serial data and the clock signals which are output (bit clock and symbol clock). The
setup time (t_setup) and hold time (t_hold) can be found in the data sheet.
External parallel data
When parallel data for "Custom Digital Modulation" is being fed in via the AUX I/O inter-
face (D0 – D9), the internal symbol clock is used.
The symbol clock is output on the CLOCK OUT connector (rear panel, choice of bit clock
or symbol clock) and on the SYMBCLK pin on the AUX I/O interface. Optimum timing is
achieved by using the symbol clock on the SYMBCLK pin on the AUX I/O interface. The
setup and hold times (see following diagram, tsetup and thold) that must be maintained
in the R&S Signal Generator to ensure that the serial data is accepted correctly can be
found in the data sheet.
The following diagram illustrates the timing ratios between data and clock when parallel
data is being supplied from an external source and the internal clock source is being used.
Fig. 5-30: External parallel data, internal clock signal and the clock signal that is output on the AUX I/
O interface The setup time (t_setup) and hold time (t_hold) can be found in the data sheet.
External Clock and External Synchronous Data
When synchronous modulation data is being fed in from an external source for "Custom
Digital Modulation", clock generation in the R&S Signal Generator can be synchronized
on the rising or falling edge of an external symbol clock. The clock reference is supplied
on the CLOCK connector (front panel).
The clock signals generated as a result are output on the CLOCK OUT connector (rear
panel, choice of bit clock or symbol clock) and on the BITCLK or SYMBCLK pins on the
AUX I/O interface.
External serial data
The following diagram illustrates the timing ratios between data and clock when serial
data is being supplied from an external source and an external reference clock is being
used.
Baseband Signal - Baseband Block
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