Instrument Function
R&S
®
SMU200A
334Operating Manual 1007.9845.32 ─ 15
Fig. 5-31: External serial data and external symbol clock - 3 bits/symbol with high and low active symbol
clock for marking the LSB. The data and the symbol clock must change state simulta-
neously. The setup time (tsetup) and hold time (thold) can be found in the data sheet.
A bit clock is generated from the externally supplied symbol clock and is used for reading
the serial data into the R&S Signal Generator. The active edge of this bit clock is located
ahead of the symbol clock.
External parallel data
The following diagram illustrates the timing ratios between data and clock when parallel
data is being supplied from an external source and an external reference clock is being
used.
Fig. 5-32: External parallel data with high and low active external symbol clock. The setup time (tsetup)
and hold time (thold) can be found in the data sheet.
The R&S Signal Generator uses the externally supplied symbol clock to generate an
internal symbol clock that defines the sampling points at which the parallel data is read
into the R&S Signal Generator. These sampling points are also located a little ahead of
the external symbol clock.
External Clock and Internal or External Asynchronous Data
If the modulation data is generated internally or supplied asynchronously from an external
source, clock generation in the R&S SMU can be synchronized on an external symbol
clock, or a multiple thereof, which is fed in on the CLOCK connector (front panel). Syn-
chronization can be based on the rising edge or falling edge according to choice. The
maximum permissible multiple symbol clock can be found in the data sheet.
5.8.2.6 Control Signals
The following control signals are processed in the R&S SMU:
●
"Burst Gate" for power ramping
●
"Level Attenuation" for power ramping
●
"CW" for controlling the CW (continuous wave) mode
The "CW" signal turns off digital modulation. The signal is output in unmodulated form.
Baseband Signal - Baseband Block
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