EasyManuals Logo

Intel Arria 10 User Manual

Intel Arria 10
607 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #142 background imageLoading...
Page #142 background image
Name Value Description
PREPREVAL
0-15
Specifies the preset Pre-tap value. The default value is 0.
INITMAINVAL Init VOD
tap Value
0-31
Specifies the initial V
OD
value. This value is set by the Initialize
command of the link training protocol, defined in Clause
72.6.10.2.3.2 of IEEE Std 802.3ap–2007. The default value is 25.
INITPOSTVAL Init Post
tap Value
0-38
Specifies the initial Post-tap value. The default value is 13.
INITPREVAL Init Pre tap
Value
0-15
Specifies the initial Pre-tap value. The default value is 3.
2.6.3.4.5. Speed Detection Parameters
Selecting the speed detection option gives the PHY the ability to detect to link partners
that support 1G/10GbE but have disabled Auto-Negotiation. During Auto-Negotiation,
if AN cannot detect Differential Manchester Encoding (DME) pages from a link partner,
the Sequencer reconfigures to 1GbE and 10GbE modes (Speed/Parallel detection) until
it detects a valid 1G or 10GbE pattern.
Table 113. Speed Detection
Parameter Name Options Description
Enable automatic speed
detection
On
Off
When you turn this option On, the core includes the Sequencer
block that sends reconfiguration requests to detect 1G or 10GbE
when the Auto Negotiation block is not able to detect AN data.
Avalon-MM clock frequency
100-162 MHz Specifies the clock frequency for phy_mgmt_clk.
Link fail inhibit time for
10Gb Ethernet
504 ms Specifies the time before link_status is set to FAIL or OK. A
link fails if the link_fail_inhibit_time has expired before
link_status is set to OK. The legal range is 500-510 ms. For
more information, refer to "Clause 73 Auto Negotiation for
Backplane Ethernet" in IEEE Std 802.3ap-2007.
Link fail inhibit time for
1Gb Ethernet
40-50 ms Specifies the time before link_status is set to FAIL or OK . A
link fails if the link_fail_inhibit_time has expired before
link_status is set to OK. The legal range is 40-50 ms.
Enable PCS-Mode port On
Off
Enables or disables the PCS-Mode port.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
142

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the Intel Arria 10 and is the answer not in the manual?

Intel Arria 10 Specifications

General IconGeneral
Transceiver Data RateUp to 17.4 Gbps
Transceiver Protocols SupportedCPRI, JESD204B
Transceiver Power ConsumptionVaries depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver FeaturesClock data recovery
Power Consumption per ChannelVaries depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver TypeFPGA integrated transceiver
Operating Temperature Range-40°C to 100°C (Industrial)
Number of Transceiver Channelsup to 96 full-duplex

Related product manuals