Intel Arria 10 User Manual

• Model 2: Acknowledgment Model on page 427
• PLLs and Clock Networks on page 347
• Arria 10 Transceiver Register Map
6.8. Steps to Perform Dynamic Reconfiguration
You can dynamically reconfigure blocks in the transceiver channel or PLL through the
reconfiguration interface.
The following procedure shows the steps required to reconfigure the channel and PLL
blocks.
1. Enable dynamic reconfiguration in the IP.
2. Enable the desired configuration file formats in the IP.
3. Enable the desired dynamic reconfiguration features (such as multiple
reconfiguration profiles, including PMA analog settings in configuration files) or
feature blocks (such as embedded reconfiguration streamer and ADME).
4. If you are using:
• Direct reconfiguration flow—Refer to the register map for feature address and
valid value of write data for the feature.
• IP guided reconfiguration flow—Note the settings of the base configuration and
generate the corresponding configuration files. Note the settings of the
modified configuration and generate the corresponding configuration files. Find
out the differences in settings between the base and modified configurations.
• IP guided reconfiguration flow using multiple profiles—Create and store the
parameter settings between the various configurations or profiles using
configuration files. Find out the differences in settings between the various
configurations or profiles using configuration files.
• IP guided reconfiguration flow using the embedded streamer—Refer to the
control and status register map of the embedded reconfiguration streamer to
stream the desired profile settings.
• Reconfiguration flow for special cases—Refer to the lookup registers to be
accessed for each special case, such as TX PLL switching, TX PLL reference
clock switching, and RX CDR reference clock switching.
5. Place the channels in digital reset either simultaneously or one after another. For
details about placing the channel in reset, refer to "Model 1: Default Model" and
"Model 2: Acknowledgment Model" in the Resetting Transceiver Channels chapter.
If you are reconfiguring:
• PLLs—Place the channel transmitter associated with the PLL in reset (digital).
• TX simplex channels—Place the TX channels being reconfigured in reset
(digital).
• RX simplex channels—Place the RX channels being reconfigured in reset
(digital).
• Duplex channels—Place the channel TX and RX being reconfigured in reset
(digital).
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
Intel
®
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex