EasyManuals Logo
Home>Intel>Transceiver>Arria 10

Intel Arria 10 User Manual

Intel Arria 10
607 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #542 background imageLoading...
Page #542 background image
6.14. Dynamic Reconfiguration Interface Merging Across Multiple
IP Blocks
Dynamic reconfiguration interfaces may need to be shared between multiple IP blocks
to maximize transceiver channel utilization. The Native PHY provides the ability to
create channels that are either simplex or duplex instances. However, each physical
transceiver channel in Arria 10 devices is fully duplex.
You can share the reconfiguration interfaces across different IP blocks by manually
making a QSF assignment. There are two cases where a dynamic reconfiguration
interface might need to be shared between multiple IP blocks:
Independent instances of simplex receivers and transmitters in the same physical
location
Separate CMU PLL and TX channel in the same physical location
The following example shows one Native PHY IP instance of a TX-only channel and
another instance of an RX-only channel.
Figure 278. Independent Instances of Simplex TX/RX in the Same Physical Location
Reconfiguration
Interface 0
TX Channel
RX Channel
User Logic
Native PHY IP Core
Native PHY IP Core
Logical
User Logic
Native PHY IP Core
Physical
TX Channel
RX Channel
Reconfiguration Interface 0 merged into
Reconfiguration Interface1
Merging QSF: from Reconfiguration Interface 0
to Reconfiguration Interface 1
Reconfiguration
Interface 1
Reconfiguration
Interface 1
The following example shows one Native PHY IP instance of a TX-only channel and an
instance of a CMU PLL.
Figure 279. Separate CMU PLL and TX Channel in the Same Physical Location
CMU
TX Channel
User Logic
Transceiver PLL IP Core
Native PHY IP Core
Logical
User Logic
Native PHY IP Core
Physical
CMU
TX Channel
Reconfiguration Interface 1 merged into
Reconfiguration Interface 0
Merging QSF: from Reconfiguration Interface 1
to Reconfiguration Interface 0
Reconfiguration
Interface 0
Reconfiguration
Interface 0
Reconfiguration
Interface 1
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
542

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the Intel Arria 10 and is the answer not in the manual?

Intel Arria 10 Specifications

General IconGeneral
BrandIntel
ModelArria 10
CategoryTransceiver
LanguageEnglish

Related product manuals