Intel Arria 10 User Manual

Table 2. Data Rates Supported by GT Transceiver Channel Type
Device Variant
(4)
Data Rates
(5), (2)
Chip-to-Chip Backplane
GT 1.0 Gbps to 25.8 Gbps 1.0 Gbps to 12.5 Gbps
Note: The device data rates depend on the device speed grade. Refer to IntelArria 10 Device
Datasheet for details on available speed grades and supported data rates.
Related Information
• IntelArria 10 Device Datasheet
• IntelArria 10 Device Overview
1.1. Device Transceiver Layout
Figure 1. Arria 10 FPGA Architecture Block Diagram
The transceiver channels are placed on the left side periphery in most Arria 10 devices. For larger Arria 10
devices, additional transceiver channels are placed on the right side periphery.
Core Logic Fabric
M20K Internal Memory Blocks
Transceiver Channels
Hard IP Per Transceiver: Standard PCS, PCIe Gen3 PCS, Enhanced PCS
PCI Express Gen3 Hard IP
PLLs
M20K Internal Memory Blocks
PCI Express Gen3 Hard IP
Variable Precision DSP Blocks
I/O PLLs
Hard Memory Controllers, General-Purpose I/O Cells, LVDS
M20K Internal Memory BlocksM20K Internal Memory Blocks
Variable Precision DSP Blocks
Core Logic Fabric
I/O PLLs
Hard Memory Controllers, General-Purpose I/O Cells, LVDS
M20K Internal Memory BlocksM20K Internal Memory Blocks
Variable Precision DSP Blocks
Transceiver Channels
PCI Express Gen3 Hard IP PCI Express Gen3 Hard IP
PLLs
Hard IP Per Transceiver: Standard PCS, PCIe Gen3 PCS, Enhanced PCS
(4)
For GT device variants, the maximum transceiver data rates are specified for (-1) transceiver
speed grade.
(5)
Because the GT transceiver channels are designed for peak performance, they do not have a
reduced power mode of operation.
1. Arria
®
10 Transceiver PHY Overview
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
9

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English