Intel Arria 10 User Manual

2.7.7. ATX PLL IP Parameter Core Settings for PIPE
Table 189. Parameters for Arria 10 ATX PLL IP core in PIPE Gen1, Gen2, Gen3 modes
This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10
Transceiver Native PHY IP Core for the full range of parameter values.
Parameter Gen1 PIPE Gen2 PIPE Gen3 PIPE (For Gen3
speed)
PLL
General
Message level for rule violations Error Error Error
Protocol Mode PCIe Gen 1 PCIe Gen 2 PCIe Gen 3
Bandwidth Low, medium, high Low, medium, high Low, medium, high
Number of PLL reference clocks 1 1 1
Selected reference clock source 0 0 0
Ports
Primary PLL clock output buffer GX clock output buffer GX clock output buffer GX clock output buffer
Enable PLL GX clock output port Enable Enable Enable
Enable PLL GT clock output port Disable Disable Disable
Enable PCIe clock output port
pll_pcie_clk
Enable Enable Disable (Use the pll_pcie_clk
output port from the fPLL to
drive the hclk)
Enable ATX to fPLL cascade clock output
port
Disable Disable Disable
Output Frequency
PLL output frequency 2500MHz 2500MHz 4000MHz
PLL output datarate 2500Mbps 5000Mbps 8000Mbps
Enable fractional mode Disable Disable Disable
PLL integer reference clock frequency 100MHz, 125MHZ 100MHz, 125MHZ 100MHz, 125MHZ
Configure counters manually Disable Disable Disable
Multiple factor (M counter) N/A N/A N/A
Divide factor (N counter) N/A N/A N/A
Divide factor (L counter) N/A N/A N/A
Master Clock Generation Block
MCGB
Include master clock generation block Disable for x1
Enable for x2, x4, x8
Disable for x1
Enable for x2, x4, x8
Disable for x1
Enable for x2, x4, x8
Clock division factor N/A for x1
1 for x2, x4, x8
N/A for x1
1 for x2, x4, x8
N/A for x1
1 for x2, x4, x8
Enable x6/xN non-bnded high speed
clock output port
N/A for x1
Disable for x2, x4, x8
N/A for x1
Disable for x2, x4, x8
N/A for x1
Disable for x2, x4, x8
Enable PCIe clock switch interface N/A for x1
Disable for x2, x4, x8
N/A for x1
Enable for x2, x4, x8
N/A for x1
Enable for x2, x4, x8
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
255

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English