Intel Arria 10 User Manual

Figure 64. Block Lock Assertion
This figure shows the assertion on rx_enh_blk_lock signal when the Receiver detects the block delineation.
0707070707070707h
FFh
0h 1h
0100009C0100009Ch 0707070707070707h
11h FFh
rx_ready
0h 1h
tx_parallel_data
tx_control
rx_parallel_data
rx_control
rx_enh_highber
rx_enh_block_lock
The following figures show Idle insertion and deletion.
Figure 65. IDLE Word Insertion
This figure shows the insertion of IDLE words in the receiver data stream.
Idle Inserted
Before Insertion
After Insertion
FD000000000004AEh BBBBBB9CDDDDDD9Ch 0707070707070707h 00000000000000FBh
FD000000000004AEh BBBBBB9CDDDDDD9Ch 00000000000000FBh AAAAAAAAAAAAAAAAh
rx_parallel_data[79:0]
rx_parallel_data[79:0]
Figure 66. IDLE Word Deletion
This figure shows the deletion of IDLE words from the receiver data stream.
00000000000004ADh 00000000000004AEh
0707070707FD0000h 000000FB07070707h
00000000000004ADh 00000000000004AEh
0707070707FD0000h
AAAAAAAA000000FBh
Idle Deleted
Before Deletion
After Deletion
rx_parallel_data[79:0]
rx_parallel_data[79:0]
Figure 67. OS Word Deletion
This figure shows the deletion of Ordered set word in the receiver data stream.
OS Deleted
Before Deletion
After Deletion
FD000000000004AEh 000000FBDDDDDD9Ch AAAAAAAA00000000h 00000000AAAAAAAAh
FD000000000004AEh DDDDDD9CDDDDDD9Ch 00000000000000FBh AAAAAAAAAAAAAAAAh
rx_parallel_data[79:0]
rx_parallel_data[79:0]
2.6.3. 10GBASE-KR PHY IP Core
The 10GBASE-KR Ethernet PHY IP core supports the following features of Ethernet
standards:
• Auto negotiation for backplane Ethernet as defined in Clause 73 of the IEEE 802.3
2008 Standard. The 10GBASE-KR Ethernet PHY IP Function can auto negotiate
between 1000BASE-X, 1000BASE-KR , and 1000BASE-KR with FEC.
• 10GBASE-KR Ethernet protocol with link training as defined in Clause 72 of the
IEEE 802.3 2008 Standard. In addition to the link-partner TX tuning as defined in
Clause 72, this PHY also automatically configures the local device RX interface to
achieve less than 10
-12
bit error rate (BER) target.
• Gigabit Media Independent Interface (GMII) to connect PHY with media access
control (MAC) as defined in Clause 35 of the IEEE 802.3 2008 Standard
• Forward Error Correction (FEC) as defined in Clause 74 of the IEEE 802.3 2008
Standard
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
135

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex