Intel Arria 10 User Manual

Native PHY Port Description Address Bits
cdr_refclk3 Represents logical refclk3.
Lookup register x16D[7:0]
stores the mapping from logical
refclk3 to the physical refclk.
0x16D (Lookup Register) [7:0]
cdr_refclk4 Represents logical refclk4.
Lookup register x16E[7:0]
stores the mapping from logical
refclk4 to the physical refclk.
0x16E (Lookup Register) [7:0]
N/A CDR refclk selection MUX. 0x141 [7:0]
When performing a reference clock switch, note the logical reference clock to switch to
and the respective address and bits. After determining the logical reference clock,
follow this procedure to switch to the selected CDR reference clock:
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Read from the lookup register and save the required 8-bit pattern. For example,
switching to logical refclk3 requires saving bits[7:0] at address 0x16D.
3.
Perform a read-modify-write to bits [7:0] at address 0x141 using the 8-bit value
obtained from the lookup register.
4. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Related Information
Steps to Perform Dynamic Reconfiguration on page 516
6.12. Changing PMA Analog Parameters
You can use the reconfiguration interface on the Transceiver Native PHY IP core to
change the value of PMA analog features.
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
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Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English