Intel Arria 10 User Manual

6.1. Reconfiguring Channel and PLL Blocks
The following table lists some of the available dynamic reconfiguration features in
Arria 10 devices.
Table 262. Arria 10 Dynamic Reconfiguration Feature Support
Reconfiguration Features
Channel Reconfiguration PMA analog features
• V
OD
• Pre-emphasis
• Continuous Time Linear Equalizer (CTLE)
• Decision Feedback Equalization (DFE)
TX PLL
• TX local clock dividers
• TX PLL switching
RX CDR
• RX CDR settings
• RX CDR reference clock switching
Reconfiguration of PCS blocks within the datapath
Datapath switching
• Standard, Enhanced, PCS Direct
PLL Reconfiguration PLL settings
• Counters
PLL reference clock switching
Related Information
Unsupported Features on page 563
6.2. Interacting with the Reconfiguration Interface
Each transceiver channel and PLL contains an Avalon Memory-Mapped (Avalon-MM)
reconfiguration interface. The reconfiguration interface provides direct access to the
programmable space of each channel and PLL. Communication with the channel and
PLL reconfiguration interface requires an Avalon-MM master. Because each channel
and PLL has its own dedicated Avalon-MM interface, you can dynamically modify
channels either concurrently or sequentially, depending on how the Avalon-MM master
is connected to the Avalon-MM reconfiguration interface.
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
Intel
®
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English