b. Analog Parameters
c. Advanced Options Parameters
5. Click Finish to generate your customized XAUI PHY IP core.
Related Information
• Using the Arria 10 Transceiver Native PHY IP Core on page 45
• XAUI PHY General Parameters on page 222
• Analog Parameter Settings on page 585
• XAUI PHY Advanced Options Parameters on page 222
2.6.6.7.1. XAUI PHY General Parameters
This section describes the settings available on the General Options tab.
Table 169. General Options
Name Value Description
Device family Arria 10 The target device family.
XAUI interface type Soft XAUI Implements the PCS in soft logic and the PMA in
hard logic. Includes four channels.
Enable Sync-E support On / Off Shows separate reference clocks for CDR PLL
and TX PLL.
Number of XAUI interfaces 1 Specifies the number of XAUI interfaces. Only 1
is available in the current release.
2.6.6.7.2. XAUI PHY Advanced Options Parameters
This section describes the settings available on the Advanced Options tab.
Table 170. Advanced Options
Name Value Description
Include control and status
ports
On / Off If you turn this option on, the top-level IP core includes the
status signals and digital resets shown in XAUI Top-Level Signals
—Soft PCS and PMA and XAUI Top-Level Signals—Hard IP PCS
and PMA. If you turn this option off, you can access control and
status information using the Avalon-MM interface to the control
and status registers. The default setting is off.
Enable dynamic
reconfiguration
On / Off When you turn this option on, you can connect the dynamic
reconfiguration ports to an external reconfiguration module.
Enable rx_recovered_clk pin On / Off When you turn this option on, the RX recovered clock signal is an
output signal.
Enable phase compensation
FIFO
On / Off Enables the phase compensation FIFO to allow different clocks on
the xgmii interface.
2.6.6.8. XAUI PHY Ports
The following figure illustrates the top-level signals of the XAUI PHY IP core for the
soft IP implementation.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
222