Intel Arria 10 - How Do I Reset; Model 1: Default Model

Note: To successfully complete the calibration process, the reference clocks driving the PLLs
(ATX PLL, fPLL, CDR/CMU PLL) must be stable and free running at start of FPGA
configuration. Otherwise, recalibration is necessary.
Related Information
• Arria 10 Pin Connection Guidelines
• Calibration on page 567
For more information about the calibration process
4.3. How Do I Reset?
You reset a transceiver PHY or PLL by integrating a reset controller in your system
design to initialize the PCS and PMA blocks. You can save time by using the Intel-
provided Transceiver PHY Reset Controller IP core, or you can implement your own
reset controller that follows the recommended reset sequence. You can design your
own reset controller if you require individual control of each signal for reset or need
additional control or status signals as part of the reset functionality.
You can choose from two models for resetting the transceivers, based on your
applications:
• Model 1—Default model (Minimum Assertion Time Requirement)
Choose the Arria 10 Default Settings preset for the Transceiver PHY Reset
Controller IP.
The chapter Transceiver Reset Control in Arria 10 Devices explains the default
model in detail.
• Model 2—Acknowledgment model
This model uses an event-driven mechanism. The model is used for applications
with strict timing requirements.
4.3.1. Model 1: Default Model
4.3.1.1. Recommended Reset Sequence
How to Enable Model 1
Choose the Figure 200 on page 419 for the Transceiver PHY Reset Controller IP. This
populates the reset duration fields with the correct values required by the transceiver
reset sequencer (TRS).
4. Resetting Transceiver Channels
UG-01143 | 2018.06.15
Intel
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10 Transceiver PHY User Guide
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