Figure 218. Combining Multiple PHY Status Signals
AND
tx_cal_busy signals
from channels
To reset controller
tx_cal_busy input port
OR
Note:
This configuration also applies to the rx_cal_busy signals.
When using multiple PLLs, you can logical AND the pll_locked signals feeding the
reset controller. Similarly, you can logical OR the pll_cal_busy signals to the reset
controller tx_cal_busy port as shown below.
Figure 219. Multiple PLL Configuration
AND
pll_lock signals
from PLLs
To reset controller
pll_locked input port
AND
pll_cal_busy and
tx_cal_busy
signals
To reset controller
tx_cal_busy input port
OR
Resetting different channels separately requires multiple reset controllers. For
example, a group of channels configured for Interlaken requires a separate reset
controller from another group of channels that are configured for optical
communication.
4.7. Timing Constraints for Bonded PCS and PMA Channels
For designs that use TX PMA and PCS Bonding, the digital reset signal
(tx_digitalreset) to all TX channels within a bonded group must meet a
maximum skew tolerance imposed by physical routing. This skew tolerance is one-half
the TX parallel clock cycle (tx_clkout). This requirement is not necessary for TX
PMA Bonding or for RX PCS channels.
Note: If the design is not able to meet the maximum skew tolerance requirement with a
positive margin, Intel recommends reassigning the channels locations that are not
adjacent to the PCIe Hard IP block.
4. Resetting Transceiver Channels
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
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