Intel Arria 10 User Manual

To check if the calibration process is running, do one of the following:
•
Monitor the pll_cal_busy, tx_cal_busy, and rx_cal_busy signals.
•
Read the *_cal_busy signal status from the capability registers.
The *_cal_busy signals remain asserted as long as the calibration process is
running. To check whether or not calibration is done, you can read the capability
registers or check the *_cal_busy signals. The reconfig_waitrequest from the
Avalon-MM reconfiguration interface is not a reliable indicator to check whether or not
calibration is done. If you write 0x2 to 0x0 during calibration, PreSICE can stop the
calibration process and return the internal configuration bus back to you; therefore,
calibration is not done while the reconfig_waitrequest is low. The PMA
tx_cal_busy and rx_cal_busy are from the same internal node which cannot be
separated from the hardware. Configure the capability register 0x281[5:4] to enable
or disable tx_cal_busy or rx_cal_busy individually through the Avalon-MM
reconfiguration interface.
Related Information
• Arbitration on page 512
• Avalon Interface Specifications
• Reconfiguration Interface and Dynamic Reconfiguration Chapter on page 502
7.2. Calibration Registers
The Arria 10 transceiver PMA and PLLs include the following types of registers for
calibration:
• Avalon-MM interface arbitration registers
• Calibration enable registers
• Capability registers
• Rate switch flag registers
The Avalon-MM interface arbitration registers enable you to request internal
configuration bus access.
The PMA and PLL calibration enable registers for user recalibration are mapped to
offset address 0x100. All calibration enable registers are self-cleared after the
calibration process is completed.
The tx_cal_busy, rx_cal_busy, ATX PLL pll_cal_busy, and fPLL
pll_cal_busy signals are available from the capability registers.
The rate switch flag registers are only used for CDR rate change.
7.2.1. Avalon-MM Interface Arbitration Registers
Table 296. Avalon-MM Interface Arbitration Registers
Bit Offset Address Description
[0] 0x0
(64)
This bit arbitrates the control of Avalon-MM interface.
continued...
7. Calibration
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex