Intel Arria 10 User Manual

• Read-Modify-Write 0x1 to offset address 0x126[0] of the fPLL to select internal
feedback.
• Read-Modify-Write 0x1 to offset address 0x100 of the fPLL, then Read-Modify-
Write 0x1 to offset address 0x000 of the fPLL to request PreSICE to recalibrate
the fPLL.
• Monitor bit 1 of offset address of 0x280 of the fPLL and wait until this bit
changes to zero. This indicates recalibration is completed. Ensure the fPLL
achieves lock.
• Read-Modify-Write 0x0 to offset address 0x126[0] of the fPLL to select the
external feedback path.
3. Monitor the fPLL lock signal, wait until the fPLL achieves lock.
Related Information
• User Recalibration on page 576
• Implementing PLL Cascading on page 408
3.11. Using PLLs and Clock Networks
In Arria 10 devices, PLLs are not integrated in the Native PHY IP core. You must
instantiate the PLL IP cores separately. Unlike in previous device families, PLL merging
is no longer performed by the Quartus Prime software. This gives you more control,
transparency, and flexibility in the design process. You can specify the channel
configuration and PLL usage.
Related Information
PLLs and Clock Networks on page 347
3.11.1. Non-bonded Configurations
In a non-bonded configuration, only the high speed serial clock is routed from the
transmitter PLL to the transmitter channel. The low speed parallel clock is generated
by the local clock generation block (CGB) present in the transceiver channel. For non-
bonded configurations, because the channels are not related to each other and the
feedback path is local to the PLL, the skew between channels cannot be calculated.
Also, the skew introduced by the clock network is not compensated.
3.11.1.1. Implementing Single Channel x1 Non-Bonded Configuration
In x1 non-bonded configuration, the PLL source is local to the transceiver bank and
the x1 clock network is used to distribute the clock from the PLL to the transmitter
channel.
For a single channel design, a PLL is used to provide the clock to a transceiver
channel.
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
®
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex