Intel Arria 10 User Manual

Related Information
• Analog Parameter Settings on page 585
• Arria 10 Pin Connection Guidelines
2.2.12. Compile the Design
To compile the transceiver design, add the <phy_instancename>.qip files for all the IP
blocks generated using the IP Catalog to the Quartus Prime project library. You can
alternatively add the .qsys and .qip variants of the IP cores.
Note: If you add both the .qsys and the .qip file into the Quartus Prime project, the
software generates an error.
Related Information
Intel Quartus Prime Incremental Compilation for Hierarchical and Team-Based Design
For more information about compilation details.
2.2.13. Verify Design Functionality
Simulate your design to verify the functionality of your design. For more details, refer
to Simulating the Native Transceiver PHY IP Core section.
Related Information
• Simulating the Transceiver Native PHY IP Core on page 325
• Quartus Prime Handbook - Volume 3: Verification
Information about design simulation and verification.
2.3. Arria 10 Transceiver Protocols and PHY IP Support
Table 8. Arria 10 Transceiver Protocols and PHY IP Support
Protocol Transceiver PHY IP
Core
PCS Support Transceiver
Configuration Rule
(9)
Protocol Preset
(10)
PCIe Gen3 x1, x2, x4,
x8
Native PHY IP core
(PIPE)/Hard IP for PCI
Express
(11)
Standard and Gen3 Gen3 PIPE PCIe PIPE Gen3 x1
PCIe PIPE Gen3 x8
PCIe Gen2 x1, x2, x4,
x8
Native PHY IP (PIPE)
core/Hard IP for PCI
Express
(11)
Standard Gen2 PIPE PCIe PIPE Gen2 x1
PCIe PIPE Gen2 x8
PCIe Gen1 x1, x2, x4,
x8
Native PHY IP (PIPE)
core/Hard IP for PCI
Express
(11)
Standard Gen1 PIPE User created
continued...
(9)
For more information about Transceiver Configuration Rules, refer to Using the Intel Arria
10Transceiver Native PHY IP Core section.
(10)
For more information about Protocol Presets, refer to Using the Intel Arria 10Transceiver
Native PHY IP Core section.
(11)
Hard IP for PCI Express is also available as a separate IP core.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
41

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex