Intel Arria 10 User Manual

Figure 114. x4 Configuration with the Master Channel not Adjacent to a Hard IP
The figure below shows the placement of a x4 PIPE configuration with the Logical PCS Master Channel that is
not adjacent to a Hard IP.
ATX
PLL
Master CGB
fPLL
ATX
PLL
Master CGB
fPLL
ATX
PLL
Master CGB
fPLL
ATX
PLL
Master CGB
fPLL
ATX
PLL
Master CGB
fPLL
ATX
PLL
Master CGB
fPLL
CH5
CH4
CH3
CH2
CH1
CH0
CH5
CH4
CH3
CH2
CH1
CH0
CH5
CH4
CH3
CH2
CH1
CH0
Hard
Data CH
Master CH
Data CH
Data CH
3
2
1
0
Logical
Channel
Physical
Channel
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
IP
2.7.13. PHY IP Core for PCIe (PIPE) Link Equalization for Gen3 Data Rate
Gen3 mode requires TX and RX link equalization because of the data rate, the channel
characteristics, receiver design, and process variations. The link equalization process
allows the Endpoint and Root Port to adjust the TX and RX setup of each lane to
improve signal quality. This process results in Gen3 links with a receiver Bit Error Rate
(BER) that is less than 10
-12
.
For detailed information about the four-stage link equalization procedure for 8.0 GT/s
data rate, refer to Section 4.2.3 in the PCI Express Base Specification, Rev 3.0. A new
LTSSM state, Recovery.Equalization with Phases 0–3, reflects progress through Gen3
equalization. Phases 2 and 3 of link equalization are optional. Each link must progress
through all four phases, even if no adjustments occur. If you skip Phases 2 and 3, you
speed up link training at the expense of link BER optimization.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
274

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex