Intel Arria 10 - Page 273

Figure 113. x4 Configuration with the Master Channel Adjacent to a Hard IP
The figure below shows the placement of a x4 PIPE configuration with the Logical PCS Master Channel that is
adjacent to a Hard IP.
ATX
PLL
Master CGB
fPLL
ATX
PLL
Master CGB
fPLL
ATX
PLL
Master CGB
fPLL
ATX
PLL
Master CGB
fPLL
ATX
PLL
Master CGB
fPLL
ATX
PLL
Master CGB
fPLL
CH5
CH4
CH3
CH2
CH1
CH0
CH5
CH4
CH3
CH2
CH1
CH0
CH5
CH4
CH3
CH2
CH1
CH0
Data CH
Master CH
Data CH
Data CH
3
2
1
0
Logical
Channel
Physical
Channel
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Hard
IP
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
273