Intel Arria 10 User Manual

2.6.4.13. TimeQuest Timing Constraints
To pass timing analysis, you must decouple the clocks in different time domains. The
necessary Synopsys Design Constraints File (.sdc) timing constraints are included in
the top-level wrapper file.
2.6.5. 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core
2.6.5.1. About 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core
The 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP core implements the Ethernet
protocol as defined in Clause 36 of the IEEE 802.3 2005 Standard. The PHY IP core
consists of a physical coding sublayer (PCS) function and an embedded physical media
attachment (PMA). You can dynamically switch the PHY operating speed.
Figure 79. Block Diagram of the PHY IP Core
125-MHz
Reference Clock
Soft PCS Hard PCS
PMA
Configuration
Registers
Reconfiguration Block
Avalon-MM
Interface
TX
GMII / XGMII
1G/2.5G/5G/10G Multi-rate Ethernet PHY
Native PHY Hard IP
TX Serial
RX Serial
Hard IP
Soft Logic
Legend
Intel Device with Serial Transceivers
LL Ethernet
10G MAC
User
Application
TX
Serial Clock
PLL
for 1 GbE
PLL
for 2.5 GbE
PLL
for 10 GbE
RX
GMII / XGMII
322-MHz
Reference Clock
External
PHY
RX CDR
Reference
Clock
Transceiver
Reset
Controller
Related Information
• Using the Arria 10 Transceiver Native PHY IP Core on page 45
• Recommended Reset Sequence on page 418
• Low Latency Ethernet 10G MAC User Guide
Describes the Low Latency Ethernet 10G MAC IP Core.
2.6.5.1.1. Features
Table 151. PHY Features
Feature Description
Multiple operating speeds 1G, 2.5G, 5G, and 10G.
MAC-side interface 16-bit GMII for 1G and 2.5G.
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
199

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English