Intel Arria 10 User Manual

The following simulation flows are available:
• NativeLink—This flow simplifies simulation by allowing you to start a simulation
from the Quartus Prime software. This flow automatically creates a simulation
script and compiles design files, IP simulation model files, and Intel simulation
library models.
Note: The Quartus Prime Pro Edition software does not support NativeLink RTL
simulation
• Scripting IP Simulation—In this flow you perform the following actions:
1. Run the ip-setup-simulation utility to generate a single simulation script that
compiles simulation files for all the underlying IPs in your design. This script
needs to be regenerated whenever you upgrade or modify IPs in the design.
2. You create a top-level simulation script for compiling your testbench files and
simulating the testbench. It sources the script generated in the first action.
You do not have to modify this script even if you upgrade or modify the IPs in
your design.
• Custom Flow—This flow allows you to customize simulation for more complex
requirements. You can use this flow to compile design files, IP simulation model
files, and Intel simulation library models manually.
You can simulate the following netlist:
• The RTL functional netlist—This netlist provides cycle-accurate simulation using
Verilog HDL, SystemVerilog, and VHDL design source code. Intel and third-party
EDA vendors provide the simulation models.
Prerequisites to Simulation
Before you can simulate your design, you must have successfully passed Quartus
Prime Analysis and Synthesis.
Related Information
Simulating Intel FPGA Designs
2.10.1. NativeLink Simulation Flow
The NativeLink settings available in the Quartus Prime software allow you to specify
your simulation environment, simulation scripts, and testbenches. The Quartus Prime
software saves these settings in your project. After you specify the NativeLink
settings, you can start simulations easily from the Quartus Prime software.
2.10.1.1. How to Use NativeLink to Specify a ModelSim Simulation
Complete the following steps to specify the directory path and testbench settings for
your simulator:
1. On the Tools menu, click Options, and then click EDA Tool Options.
2. Browse to the directory for your simulator. The following table lists the directories
for supported simulators:
Table 225.
Simulator Path
Simulator Path
Mentor Graphics* ModelSim - Intel FPGA Edition <drive>:\<simulator install path>\win32aloem (Windows)
2. Implementing Protocols in Arria 10 Transceivers
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex