Intel Arria 10 User Manual

2.4.1. Presets
You can select preset settings for the Native PHY IP core defined for each protocol. Use
presets as a starting point to specify parameters for your specific protocol or
application.
To apply a preset to the Native PHY IP core, double-click on the preset name. When
you apply a preset, all relevant options and parameters are set in the current instance
of the Native PHY IP core. For example, selecting the Interlaken preset enables all
parameters and ports that the Interlaken protocol requires.
Selecting a preset does not prevent you from changing any parameter to meet the
requirements of your design. Any changes that you make are validated by the design
rules for the transceiver configuration rules you specified, not the selected preset.
Note: Selecting a preset clears any prior selections user has made so far.
2.4.2. General and Datapath Parameters
You can customize your instance of the Native PHY IP core by specifying parameter
values. In the Parameter Editor, the parameters are organized in the following
sections for each functional block and feature:
• General, Common PMA Options, and Datapath Options
• TX PMA
• RX PMA
• Standard PCS
• Enhanced PCS
• PCS Direct Datapath
• Dynamic Reconfiguration
• Analog PMA Settings (Optional)
• Generation Options
Table 9. General, Common PMA Options, and Datapath Options
Parameter Value Description
Message level for rule
violations
error
warning
Specifies the messaging level for parameter rule violations.
Selecting error causes all rule violations to prevent IP generation.
Selecting warning displays all rule violations as warnings in the
message window and allows IP generation despite the violations.
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VCCR_GXB and
VCCT_GXB supply voltage
for the Transceiver
0_9V, 1_0V, 1_1V
Selects the VCCR_GXB and VCCT_GXB supply voltage for the
Transceiver.
Note: This option is only used for GUI rule validation. Use
Quartus Prime Setting File (.qsf) assignments to set this
parameter in your static design.
Transceiver Link Type sr, lr Selects the type of transceiver link. sr-Short Reach (Chip-to-chip
communication), lr-Long Reach (Backplane communication).
continued...
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Although you can generate the PHY with warnings, you can not compile the PHY in Quartus
Prime.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
48

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex