Intel Arria 10 User Manual

2.7.4. How to Implement PCI Express (PIPE) in Arria 10 Transceivers
You must be familiar with the Standard PCS architecture, Gen3 PCS architecture, PLL
architecture, and the reset controller before implementing the PCI Express protocol.
1. Go to the IP Catalog and select the Arria 10 Transceiver Native PHY IP Core.
Refer to Select and Instantiate the PHY IP Core on page 33 for more details.
2. Select Gen1/Gen2/Gen3 PIPE from the Arria 10 Transceiver configuration
rules list, located under Datapath Options.
3. Use the parameter values in the tables in Transceiver Native PHY IP Parameters for
PCI Express Transceiver Configurations Rules as a starting point. Alternatively, you
can use Arria 10 Transceiver Native PHY Presets . You can then modify the
settings to meet your specific requirements.
4. Click Finish to generate the Native PHY IP (this is your RTL file).
5. Instantiate and configure your PLL.
6. Create a transceiver reset controller. You can use your own reset controller or use
the Transceiver PHY Reset Controller.
7. Connect the Native PHY IP to the PLL IP core and the reset controller. Use the
information in Transceiver Native PHY IP Ports for PCI Express Transceiver
Configuration Rules to connect the ports.
8. Simulate your design to verify its functionality.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
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Arria
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex