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Intel Arria 10 User Manual

Intel Arria 10
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Word
Addr
Bits R/W Register Name Description
[7:0]
syncstatus[7:0]
Records the synchronization status of the
corresponding bit. The RX sync status register has 1
bit per channel for a total of 4 bits per soft XAUI link;
soft XAUI uses bits 0–3. Reading the value of the
syncstatus register clears the bits.
From block: Word aligner
0x085 [31:16] N/A Reserved N/A
[15:8] R
errdetect[7:0]
When set, indicates that a received 10-bit code group
has an 8B/10B code violation or disparity error. Use
errdetect with disperr to differentiate between a
code violation error, a disparity error, or both. There
are 2 bits per RX channel for a total of 8 bits per XAUI
link. Reading the value of the errdetect register
clears the bits.
From block: 8B/10B decoder
[7:0]
disperr[7:0]
Indicates that the received 10-bit code or data group
has a disparity error. When set, the corresponding
errdetect bits are also set. There are 2 bits per RX
channel for a total of 8 bits per XAUI link. Reading the
value of the errdetect register clears the bits.
From block: 8B/10B decoder
0x08a [0] RW
simulation_flag
Setting this bit to 1 shortens the duration of reset and
loss timer when simulating. Intel recommends that
you keep this bit set for simulation.
Related Information
Avalon Interface Specifications
2.6.6.11. XAUI PHY Timing Analyzer SDC Constraint
Refer to the "Timing Constraints for Bonded PCS and PMA Channels" section for the
Synopsis Design Constraints (SDC) for XAUI.
Related Information
Timing Constraints for Bonded PCS and PMA Channels on page 443
2.6.7. Acronyms
This table defines some commonly used Ethernet acronyms.
Table 179. Ethernet Acronyms
Acronym Definition
AN Auto-Negotiation in Ethernet as described in Clause 73 of IEEE 802.3ap-2007.
BER Bit Error Rate.
DME Differential Manchester Encoding.
FEC Forward error correction.
GMII Gigabit Media Independent Interface.
KR Short hand notation for Backplane Ethernet with 64b/66b encoding.
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General IconGeneral
BrandIntel
ModelArria 10
CategoryTransceiver
LanguageEnglish

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