Intel Arria 10 - Supported PIPE Features

Figure 91. Transceiver Channel Datapath for PIPE Gen1/Gen2/Gen3 Configurations
RX
FIFO
Byte
Deserializer
8B/10B Decoder
Rate Match FIFO
Block
Synchronizer
Rate Match
FIFO
Gearbox
Receiver PMA
Word Aligner
Deserializer
CDR
Receiver Standard PCS
Receiver Gen3 PCS
Transmitter Gen3 PCS
rx_serial_data
PRBS
Verifier
PIPE Interface
FPGA
Fabric
Transmitter Standard PCS
Transmitter PMA
Serializer
tx_serial_data
TX
FIFO
Byte Serializer
8B/10B Encoder
PRBS
Generator
TX Bit Slip
PCI Exxpress Hard IP
2.7.2. Supported PIPE Features
PIPE Gen1, Gen2, and Gen3 configurations support different features.
Table 181. Supported Features for PIPE Configurations
Protocol Feature Gen1
(2.5 Gbps)
Gen2
(5 Gbps)
Gen3
(8 Gbps)
x1, x2, x4, x8 link configurations Yes Yes Yes
PCIe-compliant synchronization state machine Yes Yes Yes
±300 ppm (total 600 ppm) clock rate compensation Yes Yes Yes
Transmitter driver electrical idle Yes Yes Yes
Receiver detection Yes Yes Yes
8B/10B encoding/decoding disparity control Yes Yes No
128b/130b encoding/decoding No No Yes (supported
through the
Gearbox)
Scrambling/Descrambling No No Yes
(implemented
in FPGA fabric)
(38)
Power state management Yes Yes Yes
Receiver PIPE status encoding pipe_rxstatus[2:0]
Yes Yes Yes
Dynamic switching between 2.5 Gbps and 5 Gbps signaling rate No Yes No
continued...
(38)
You must enable scrambling/descrambling in Gen1/Gen2 when using Arria 10 PCIe Gen3
configurations.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
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®
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