Intel Arria 10 User Manual

Protocol Feature Gen1
(2.5 Gbps)
Gen2
(5 Gbps)
Gen3
(8 Gbps)
Dynamic switching between 2.5 Gbps, 5 Gbps, and 8 Gbps
signaling rate
No No Yes
Dynamic transmitter margining for differential output voltage
control
No Yes Yes
Dynamic transmitter buffer de-emphasis of –3.5 dB and –6 dB No Yes Yes
Dynamic Gen3 transceiver pre-emphasis, de-emphasis, and
equalization
No No Yes
PCS PMA interface width (bits) 10 10 32
Receiver Electrical Idle Inference (EII) Implement in FPGA
fabric
Implement in
FPGA fabric
Implement in
FPGA fabric
Related Information
• PCIe Gen3 PCS Architecture on page 495
For more information about PIPE Gen3.
• Intel PHY Interface for the PCI Express* (PIPE) Architecture PCI Express 2.0
• Intel PHY Interface for the PCI Express (PIPE) Architecture PCI Express 3.0
2.7.2.1. Gen1/Gen2 Features
In a PIPE configuration, each channel has a PIPE interface block that transfers data,
control, and status signals between the PHY-MAC layer and the transceiver channel
PCS and PMA blocks. The PIPE configuration is based on the PIPE 2.0 specification. If
you use a PIPE configuration, you must implement the PHY-MAC layer using soft IP in
the FPGA fabric.
2.7.2.1.1. Dynamic Switching Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps)
In a PIPE configuration, Native PHY IP Core provides an input signal pipe_rate
[1:0] that is functionally equivalent to the RATE signal specified in the PCIe
specification. A change in value from 2'b00 to 2'b01 on this input signal pipe_rate
[1:0] initiates a data rate switch from Gen1 to Gen2. A change in value from 2'b01
to 2'b00 on the input signal initiates a data rate switch from Gen2 to Gen1.
2.7.2.1.2. Transmitter Electrical Idle Generation
The PIPE interface block in Arria 10 devices puts the transmitter buffer in an electrical
idle state when the electrical idle input signal is asserted. During electrical idle, the
transmitter buffer differential and common mode output voltage levels are compliant
with the PCIe Base Specification 2.0 for both PCIe Gen1 and Gen2 data rates.
The PCIe specification requires the transmitter driver to be in electrical idle in certain
power states.
Note: For more information about input signal levels required in different power states, refer
to Power State Management in the next section.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
232

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex