Intel Arria 10 User Manual

2.7.2.1.3. Power State Management
Table 182. Power States Defined in the PCIe Specification
To minimize power consumption, the physical layer device must support the following power states.
Power States Description
P0 Normal operating state during which packet data is transferred on the PCIe link.
P0s, P1, and P2 The PHY-MAC layer directs the physical layer to transition into these low-power states.
The PIPE interface in Arria 10 transceivers provides a pipe_powerdown input port for
each transceiver channel configured in a PIPE configuration.
The PCIe specification requires the physical layer device to implement power-saving
measures when the P0 power state transitions to the low power states. Arria 10
transceivers do not implement these power-saving measures except for putting the
transmitter buffer in electrical idle mode in the lower power states.
2.7.2.1.4. 8B/10B Encoder Usage for Compliance Pattern Transmission Support
The PCIe transmitter transmits a compliance pattern when the Link Training and
Status State Machine (LTSSM) enters the Polling.Compliance substate. The
Polling.Compliance substate assesses if the transmitter is electrically compliant with
the PCIe voltage and timing specifications.
2.7.2.1.5. Receiver Status
The PCIe specification requires the PHY to encode the receiver status on a 3-bit status
signal pipe_rx_status[2:0]. This status signal is used by the PHY-MAC layer for its
operation. The PIPE interface block receives status signals from the transceiver
channel PCS and PMA blocks, and encodes the status on the pipe_rx_status[2:0]
signal to the FPGA fabric. The encoding of the status signals on the
pipe_rx_status[2:0] signal conforms to the PCIe specification.
2.7.2.1.6. Receiver Detection
The PIPE interface block in Arria 10 transceivers provides an input signal
pipe_tx_detectrx_loopback for the receiver detect operation. The PCIe protocol
requires this signal to be high during the Detect state of the LTSSM. When the
pipe_tx_detectrx_loopback signal is asserted in the P1 power state, the PIPE
interface block sends a command signal to the transmitter driver in that channel to
initiate a receiver detect sequence. In the P1 power state, the transmitter buffer must
always be in the electrical idle state. After receiving this command signal, the receiver
detect circuitry creates a step voltage at the output of the transmitter buffer. The time
constant of the step voltage on the trace increases if an active receiver that complies
with the PCIe input impedance requirements is present at the far end. The receiver
detect circuitry monitors this time constant to determine if a receiver is present.
Note: For the receiver detect circuitry to function reliably, the transceiver on-chip
termination must be used. Also, the AC-coupling capacitor on the serial link and the
receiver termination values used in your system must be compliant with the PCIe Base
Specification 2.0.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
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Arria
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10 Transceiver PHY User Guide
233

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex