Intel Arria 10 User Manual

The receiver input pin drives the feedback and cascading clock network, which can
then feed any number of transmitter PLLs on the same side of the device. When a
receiver input pin is used as an input reference clock source, the clock data recovery
(CDR) block of that channel is not available. As indicated in Figure 173 on page 373,
only one RX differential pin pair per three channels can be used as an input reference
clock source at any given time.
3.2.3. PLL Cascading as an Input Reference Clock Source
In PLL cascading, PLL outputs are connected to the feedback and cascading clock
network. The input reference clock to the first PLL can be sourced from the same
network. In this mode, the output of one PLL drives the reference clock input of
another PLL. PLL cascading can generate frequency outputs not normally possible with
a single PLL solution. The transceiver in Arria 10 devices support fPLL to fPLL
cascading, with only maximum two fPLLs allowed in the cascading chain. ATX PLL to
fPLL cascading is available to OTN and SDI protocols only.
Note: • To successfully complete the calibration process, the reference clocks driving the
PLLs (ATX PLL, fPLL, CDR/CMU PLL) must be stable and free running at start of
FPGA configuration. Otherwise, recalibration is necessary.
• When the fPLL is used as a cascaded fPLL (downstream fPLL), a user recalibration
on the fPLL is required. Refer to "User Recalibration" section in "Calibration"
chapter for more information.
Related Information
Calibration on page 567
For more information about the calibration process
3.2.4. Reference Clock Network
The reference clock network distributes a reference clock source to either the entire
left or right side of the FPGA where the transceivers reside. This allows any reference
clock pin to drive any transmitter PLL on the same side of the device. Designs using
multiple transmitter PLLs which require the same reference clock frequency and are
located along the same side of the device, can share the same dedicated reference
clock (refclk) pin.
3.2.5. Global Clock or Core Clock as an Input Reference Clock
The global clock or the core clock can be used as an input reference clock for any PLL
type.
The global or core clock network routes the clock directly to the PLL. In this case the
PLL reference clock network is not used. For best performance, use the dedicated
reference clock pins or the reference clock network.
3.3. Transmitter Clock Network
The transmitter clock network routes the clock from the transmitter PLL to the
transmitter channel. It provides two types of clocks to the transmitter channel:
• High Speed Serial clock—high-speed clock for the serializer.
• Low Speed Parallel clock—low-speed clock for the serializer and the PCS.
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
375

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English