Intel Arria 10 User Manual

For example, if the base configuration of the above case is configured for the TX and
RX FIFOs in the Register Mode, the following constraint needs to be created:
•
set_false_path -from [get_registers {native:native_inst|
native_altera_xcvr_native_a10_150_lzjn6xi:xcvr_native_a10_0|
twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_nati
ve_inst|
twentynm_xcvr_native_rev_20nm5es:twentynm_xcvr_native_inst|
twentynm_pcs_rev_20nm5es:inst_twentynm_pcs|
gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_p
ld_pcs_interface~pma_tx_pma_clk_reg.reg}] -to [get_registers
<Core Logic B>]
•
set_false_path -from [get_registers {native:native_inst|
native_altera_xcvr_native_a10_150_lzjn6xi:xcvr_native_a10_0|
twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_nati
ve_inst|
twentynm_xcvr_native_rev_20nm5es:twentynm_xcvr_native_inst|
twentynm_pcs_rev_20nm5es:inst_twentynm_pcs|
gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_p
ld_pcs_interface~pma_rx_pma_clk_reg.reg}] -to [get_registers
<Core Logic B>]
Note: When the dynamic reconfiguration (multi profiles) is enabled, do not move or rename
the IP directory. Moving the IP location causes Quartus to fail to pick up the
configuration profiles. If the IP directory is changed, the default configuration can be
successfully time constrained and analyzed, but the non-default configuration has
timing issues as the timing arc may be missing.
6.18. Unsupported Features
The following features are not supported by either the Transceiver Native PHY IP core
or the PLL IP reconfiguration interface:
• Reconfiguration from a bonded configuration to a non-bonded configuration, or
vice versa
• Reconfiguration from a bonded protocol to another bonded protocol
• Reconfiguration from PCIe (with Hard IP) to PCIe (without Hard IP) or non-PCIe
bonded protocol switching
• Switching between bonding schemes, such as xN to feedback compensation
• Master CGB reconfiguration
• Switching between two master CGBs
• Serialization factor changes on bonded channels
• TX PLL switching on bonded channels
Note: Transceiver Native PHY IP non-bonded configuration to another Transceiver Native PHY
IP non-bonded configuration is supported.
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
563

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex