Intel Arria 10 User Manual

For Native PHY 1—receive-only instance to be merged with Native PHY 0:
set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to rx[0]
Related Information
Calibration on page 567
6.15. Embedded Debug Features
Note: For details on TTK usage refer to "Debugging Transceiver Links" in Quartus Prime
Standard Edition Handbook Volume 3: Verification.
The Arria 10 Transceiver Native PHY, ATX PLL, fPLL, and CMU PLL IP cores provide the
following optional debug features to facilitate embedded test and debug capability:
• Altera Debug Master Endpoint (ADME)
• Optional Reconfiguration Logic
Related Information
Quartus Prime Standard Edition Handbook Volume 3: Verification
6.15.1. Altera Debug Master Endpoint
The ADME is a JTAG-based Avalon Memory-Mapped (Avalon-MM) master that provides
access to the transceiver and PLL registers through the system console. You can
enable ADME using the Enable Altera Debug Master Endpoint option available
under the Dynamic Reconfiguration tab in the Native PHY and PLL IP cores. When
using ADME, the Quartus Prime software inserts the debug interconnect fabric to
connect with USB, JTAG, or other net hosts. Select the Share Reconfiguration
Interface parameter when the Native PHY IP instance has more than one channel.
When you enable ADME in your design, you must
• connect an Avalon-MM master to the reconfiguration interface.
•
OR connect the, reconfig_reset signals and ground the reconfig_write,
reconfig_read, reconfig_address and reconfig_write data signals of the
reconfiguration interface. If the reconfiguration interface signals are not connected
appropriately, there is no clock or reset for the ADME, and the ADME does not
function as expected.
6.15.2. Optional Reconfiguration Logic
The Arria 10 Transceiver Native PHY, ATX PLL, fPLL, and CMU PLL IP cores contain soft
logic for debug purposes known as the Optional Reconfiguration Logic. This soft logic
provides a set of registers that enable you to determine the state of the Native PHY
and PLL IP cores.
You can enable the following optional reconfiguration logic options in the transceiver
Native PHY and PLL IP cores:
• Capability registers
• Control and status registers
• PRBS soft accumulators (Native PHY IP core only)
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
544

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English